Job description for Design Verification Engineer (3+ YOE | English Speaking) at Sharework
- JD:
- Take ownership of technology-related activities within projects and offer technical direction or solutions to support successful task completion.
- Provide technical support, recommendations, and solutions to address project needs.
- Coach and support team members in strengthening their technical expertise and improving overall efficiency.
- Prepare and deliver status reports to help reduce project risks and support the resolution of escalations.
- Ensure adherence to defined processes in the assigned module and contribute to technical reviews and discussions.
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Requirements:
- Bachelor’s degree in Electronics, Electrical Engineering, or a comparable discipline.
- At least 3 years of experience working as a Design Verification Engineer or in a similar role.
- Solid knowledge of the ASIC/SoC development lifecycle.
- Hands-on experience with OVM/UVM methodologies using SystemVerilog.
- Experience creating or updating full-chip test plans.
- Experience in testbench development or enhancement, test case creation, coding, execution, bug investigation, regression runs, coverage analysis, and verification sign-off.
- Familiarity with widely used standards and protocols such as UCIe, PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C, and AMBA.
- Experience performing gate-level simulations.
- Proficiency in scripting.
- Should have contributed to several ASIC/SoC verification projects through to the tape-out phase.
- Strong English communication skills.
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Benefits:
- Salary: according to capacity, will be reviewed after one year of work.
- Work in a dynamic, creative environment with young, close colleagues.
- 13th-month salary bonus, hot bonus, salary/performance review, ...
- Social, health & unemployment insurance;
- Participate in Company and Group activities: Team building, travel, healing retreat, ...
- Opportunities for development and advancement.
