Responsibilities

Analyze device physical characteristics and performance through WAT (Wafer Acceptance Test) electrical parameters. Develop deep understanding of device physics for advanced process nodes (High-k/Metal Gate/FinFET/GAA/CFET). Conduct SPICE model Silicon-to-Simulation (S2S) analysis, WAT-to-chip performance correlation analysis, and WAT test line development. Collaborate closely with FAB and design teams to identify optimal process conditions and device structures for product performance enhancement.

Monitor product yield and conduct systematic analysis on low-yield wafers. Leverage large-scale data analytics and DOE experiments to identify yield improvement opportunities. Partner with test and manufacturing teams to drive continuous yield optimization.

Possess in-depth knowledge of advanced logic process technology and CMOS device physics. Proficiently operate TCAD simulation tools with thorough understanding of relevant process and device physics models. Independently perform process and device calibration and optimization through TCAD simulation.

Apply solid device physics knowledge to perform SPICE model parameter tuning for accurate characterization of device electrical properties and delivery of customized SPICE models. Additionally responsible for device-level testkey design.

Requirements

Recent PhD graduates or those who graduated within the past two years with a PhD from fields including but not limited to Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, or Materials Science and Engineering.

Good foundational knowledge of semiconductor device physics, integrated circuit design, and manufacturing.

Familiar with advanced process technology and strong scripting skills are preferred.

Excellent academic performance, with a strong curiosity, learning ability, and knowledge transfer capability in new areas and related professional fields.