Responsibility:

1. Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging.
2. Multiple tasks including but not limited to: back-end physical implementation from gate-level netlist to GDSII, layout design of digital/analog chips, including PV, IR signoff, PPAC optimization, and STA/Spice signoff.

Requirement:

1. Fresh graduates or those who graduated in 2024 or 2025 with a bachelor's degree or higher in fields including but not limited to Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, or Materials Science and Engineering.
2. Excellent academic performance, with a strong curiosity, learning ability, and knowledge transfer capability in new areas and related professional fields.
3. Understanding of the IC development process, with a certain theoretical foundation in digital circuits, practical skills, and innovation ability.