Design Verification Engineer

We are seeking a Design Verification Engineer to join our semiconductor development team. The successful candidate will be responsible for verifying DRAM and high-speed interface designs, developing verification environments, executing test plans, and ensuring protocol compliance through simulation and coverage-driven verification methodologies.

Responsibilities:

• Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation.
• Develop and execute design verification plans to ensure functional correctness and compliance with specifications.
• Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
• Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
• Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.
• Define and implement functional coverage.
• Perform coverage analysis and identify testing gaps.
• Develop test plan and testcases from specification document.

Requirements:

• Possess at least 3 years experiences in USB/USB2.0/USB3.0
• Strong coding with Verilog and System Verilog.
• Good knowledge of design verification methodology UVM.
• Experiences with sequence creation, functional cover groups and assertion coding.
• Strong C/C++ software development experiences.
• Familiar with scripting language, such as Perl, C shell, Makefile, Ruby,Bash, TCL.
• Familiar with AMBA protocols i.e. AXI, AHB, APB etc.
• Understanding of low power design techniques (clock gating, power gating etc

Key Skills

1. SystemVerilog
2. UVM
3. USB Verification
4. DRAM Verification
5. AXI/AHB/APB
6. Functional Coverage
7. Assertions (SVA)
8. RTL Debug
9. C/C++
10. Python / Perl / Tcl
11. Low-Power Verification (UPF)