JOB DESCRIPTION

RTL-level digital design and problem solving

Function verification and support

Work closely with backend team on Digital synthesis, place-and-route, Design for Test and Static timing analysis

Lead and guide junior engineers

Digital functional verification and FPGA verification

JOB REQUIREMENTS

Bachelor/Masters in Electronics/Electrical Engineering with Mixed Signal IC design/verification experience.

At least 7-10 Year(s) of working experience in application/ validation

Fluent in Verilog coding, design, simulation, and verification domains

Definition and implementation of custom digital interfaces (I2C, 3-wire, single_wire etc.)

Definition and implementation of custom finite state machines, register maps, control logic which interface with analog circuits such as drivers and proprietary IPs like OTP or flash memory

RTL design for synchronous and asynchronous applications, including multiple clock domains

Basic knowledge of Logic synthesis, place & route, static timing analysis, logic equivalency checking

  Usage of Cadence tools like Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus and Virtuoso will be preferred

Candidates with relevant education/experience are invited to apply for the following positions via the Quick APPLY button below.

Suitable candidates will be called for a face to face interview.

STRICTLY NO RECRUITMENT AGENT